The present invention relates generally to development of capped container structures, and in particular to development of semiconductor container capacitor structures having a dielectric cap, and apparatus making use of such container capacitor structures.
Many electronic systems include a memory device, such as a Dynamic Random Access Memory (DRAM), to store data. A typical DRAM includes an array of memory cells. Each memory cell includes a capacitor that stores the data in the cell and a transistor that controls access to the data. The capacitor includes two conductive plates. The top plate of each capacitor is typically shared, or common, with each of the other capacitors. This plate is referred to as the xe2x80x9ccell plate.xe2x80x9d The charge stored across the capacitor is representative of a data bit and can be either a high voltage or a low voltage.
Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as digit lines, which are coupled to input/output (I/O) lines through transistors used as switching devices. Typically, for each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line. Thus, each such memory cell has two digit lines, digit and digit complement.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines and memory cells are associated with the intersections of the lines. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to a word line decoder and to a digit line decoder. The word line decoder activates a word line in response to the word line address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The digit line decoder selects a digit line pair in response to the digit line address. For a read operation the selected word line activates the access transistors for a given word line address, and data is latched to the digit line pairs.
As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing memory cell area and its accompanying capacitor area, since capacitance is a function of plate area. Additionally, there is a continuing goal to further decrease memory cell area.
A principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. One common form of stacked capacitor structure is a cylindrical container stacked capacitor, with a container structure forming the bottom plate of the capacitor.
Another method of increasing cell capacitance is through the use of high surface area materials such as hemispherical grain polysilicon (HSG) which increase available surface area for a given foot print due to their roughened or irregular surfaces.
As cell area decreases, container structures must be formed in closer proximity to neighboring container structures. At close proximity, a danger exists that conductive fragments will rest on the tops of the container structures, bridging between neighboring container structures and thus acting as a short circuit. Such conductive fragments may be pieces of a container dislodged or broken off during cell formation. Fragments from HSG container structures are often referred to as xe2x80x9cgrapesxe2x80x9d or xe2x80x9cfloaters.xe2x80x9d Capacitors produced from such shorted container structures will result in defective memory cells, as the cells will be unable to accurately store data.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved container structure and methods of producing same.
One embodiment of the invention provides a semiconductor structure. The semiconductor structure includes a conductive container structure having a closed bottom and sidewalls extending upward from the closed bottom. The semiconductor container structure further includes a dielectric cap on top of the sidewalls. In another embodiment, the conductive container structure has a cylindrical shape. In a further embodiment, the conductive container structure is formed using amorphous silicon, polysilicon or hemispherical grain polysilicon, either singly or in combination. In a still further embodiment, the silicon material is conductively doped. In one embodiment, the dielectric cap is formed of oxide, nitride or silicon oxynitride. In another embodiment, the dielectric cap is annealed.
Another embodiment of the invention provides a method of forming a semiconductor structure. The method includes forming an insulating layer on a substrate and forming an opening in the insulating layer, wherein the opening has a bottom on an exposed portion of the substrate and sidewalls defined by the insulating layer. The method further includes forming a conductive layer on the insulating layer and the exposed portion of the substrate, forming a fill layer on the conductive layer, wherein the fill layer fills the opening, and removing the conductive layer and the fill layer to a level below a top of the insulating layer, thereby forming a container structure having sidewalls comprised of the conductive layer on the sidewalls of the opening, and a closed bottom comprised of the conductive layer on the bottom of the opening. The method still further includes forming a dielectric cap on a top of the sidewalls of the conductive layer, removing the fill layer to expose an inside of the container structure, and removing at least a portion of the insulating layer to expose an outside of the container structure. In one embodiment, the dielectric cap is formed by forming a dielectric layer on the insulating layer, the conductive layer and the fill layer, and removing the dielectric layer from the insulating layer and the fill layer.
A further embodiment of the invention provides a method of forming a semiconductor structure. The method includes forming an insulating layer on a substrate and forming an opening in the insulating layer, wherein the opening has a bottom on an exposed portion of the substrate and sidewalls defined by the insulating layer. The method further includes forming a conductive layer on the insulating layer and the exposed portion of the substrate, forming a fill layer on the conductive layer, wherein the fill layer fills the opening, removing the fill layer to a level substantially even with a top of the insulating layer, and removing the conductive layer to a level below the level below the top of the insulating layer, thereby forming a container structure having sidewalls comprised of the conductive layer on the sidewalls of the opening, and a closed bottom comprised of the conductive layer on the bottom of the opening. The method still further includes forming a dielectric cap on a top of the sidewalls of the conductive layer, removing the fill layer to expose an inside of the container structure, and removing at least a portion of the insulating layer to expose an outside of the container structure.
Further embodiments of the invention include semiconductor structures and methods of varying scope, as well as apparatus, devices, modules and systems making use of such semiconductor structures and methods.